a. Field
The instant invention relates to a digital pulse-width-modulator comprising a discretely adjustable delay line.
b. Background
Pulse-width-modulation (PWM) is a technique for controlling analog circuits with a digital output in which a duty cycle of a square wave is modulated to encode a specific input signal to a pulse-width modulator. PWM is employed in a wide variety of applications, ranging from measurement and communications to power control and conversion.
High resolution, high frequency digital pulse-width modulators (DPWM) can be used to control DC-DC converters and achieve features such as high bandwidth, precise regulation or elimination of limit cycling disturbances. In Syed, A et al., “Digital pulse-width modulator architectures,” IEEE PESC 2004, pp. 4689-95, Vol. 6 (2004), for example, different structures of DPWM topologies are discussed and compared.
The direct implementation of an analog pulse-width-modulator in the digital domain is a counter-based DPWM. An n-bit counter counts up by one step at each input clock period, tclk. When the counter counts to its period length, it resets itself and starts counting from the zero value at the next input clock period tclk. In such a counter-based DPWM, the required clock frequency is directly dependent on the number of bits of the counter, n, and the desired switching frequency, fsw=1/Ts as shown in the following formula.fclk=2nfsw  (1)
The advantage of a counter-based DPWM is its simplicity and linearity. For a reasonable DPWM resolution, however, the number of bits of the counter, n, is large in value. Therefore, the required clock frequency fclk can be unreasonably high. In a 10-bit DPWM implementation with a switching frequency fsw=1 MHz, for example, the required clock frequency, fclk is approximately 1 GHz. This makes the implementation of a high-resolution, high-frequency counter-based DPWM a difficult task.
Another implementation of a DPWM is a delay-line DPWM. In a pure delay line DPWM, a delay line is used to resolve the output modulated signal. While a high resolution pure delay line DPWM requires a relatively larger area and more hardware resources than a counter-based DPWM, the pure delay line DPWM can be operated with a much lower clock frequency than a counter-based DPWM.
A hybrid DPWM is a compromise between a high clock frequency of a counter-based DPWM and a large area requirement of a pure delay line DPWM. A hybrid DPWM, for example, provides a high resolution, high frequency DPWM without a need for a relatively high input clock frequency, as in a counter-based DPWM, or a relatively large area, as in a pure delay-line based DPWM.
Different topologies of hybrid DPWM have been introduced, such as a ring-oscillator DPWM without any external clock and open-loop delay-line DPWM with an external clock. A hybrid DPWM with an open-loop delay-line is based on a combination of a counter and a delay-line. The counter, for example, may provide a most-significant-bit (msb) or a least-significant-bit (lsb) portion of the duty cycle of the modulator. FIG. 1 shows an example of a hybrid DPWM 10, with a counter 12 and an open-loop delay line 14. The DPWM, in this example, is a 5-bit DPWM with a three-bit counter providing a three msb portion 16 of a duty cycle command and a two-bit delay line providing a two-bit lsb portion 18 of the duty cycle command.
As shown in FIG. 1, the counter 12 is an n-bit counter that counts at each clock period of the clock input signal, clk, to provide a counter output, cnt. The counter output cnt is compared to the three-bit msb portion 16 of the duty cycle command at a comparator 20. An output of the comparator 20, delclk, is provided to the open-loop delay-line 14. The number of delay cells, L, required in the delay-line 14 depends upon the number of bits provided by the delay-line, l, in the hybrid DPWM. In this example, the delay-line provides l=2 bits of the duty cycle command, and the number of delay cells required L=21=22=4. Thus, the open-loop delay-line 14 includes four sequential delay cells del0, del1, del2, and del3.
An L:1 multiplexer 22 taps the nodes after each of the delay cells del0, del1, del2, and del3 at inputs i0, i1, i2, and i3, respectively. The multiplexer 22 receives the two-bit lsb portion 18 of the duty cycle command and uses that portion to select one of the inputs connect the appropriate input i0, i1, i2, or i3 to the output R. The output R of the multiplexer 22 is then provided to a flip-flop 24 that then provides an output, DPWM_out.
A counter stage comprises the counter 12 and the comparator 20. The delay-line stage comprises the delay-line 14, the multiplexer 22, and the flip-flop 24.
FIG. 2 shows a timing diagram for the hybrid DPWM 10 shown in FIG. 1. In this example, the clock input signal clk is shown at the top of the timing diagram. The counter output cnt is shown just below the clock input signal clk and provides a three-bit binary counter starting at 000 and resetting itself after eight clock cycles at 111. In the example shown in FIG. 2, the duty cycle command, duty, received by the hybrid DPWM 10 is duty=10110. Thus, the three-bit msb portion 16 is msb(duty)=101 and the two-bit lsb portion 18 is lsb(duty)=10.
As described above, the counter output cnt is compared to the three-bit msb portion 16 of the duty cycle command msb(duty) at the comparator 20 to provide the resulting delclk signal shown in the timing diagram of FIG. 2. The width of the delclk signal is equivalent to one clock period of the input clock signal clk. The signal delclk is then propagated through the delay-line 14. The output of each delay cell is tapped out and connected to the L:1 multiplexer 22. The propagated signals i0-i3, from the output of the delay cells del0-del3 are also shown in the timing diagram of FIG. 2. In this example, the lsb portion of the duty cycle command lsb(duty)=10 (i.e., binary 2). Thus, the input i2 of the multiplexer 22 is selected and connected to the output R of the multiplexer. The signal R resets the output DPWM_out of the flip-flop 24.
The frequency of the output signal DPWM_out of the hybrid DPWM 10 is still determined by the formula (1) fclk=2nfsw given above, where n is the number of bits of the counter. Because a smaller n is used in a hybrid DPWM, the required input clock frequency is lower in value for a hybrid DPWM compared to a counter-based DPWM even though it provides the same DPWM resolution. In the example of FIGS. 1 and 2, for example, the required input clock frequency is four times smaller than an equivalent counter-based DPWM.
Digital Pulse-Width-Modulators with delay lines are used in many applications. In DC-DC power converters, for example, digital controllers include custom architectures and realizations of building blocks including high-resolution, high-frequency, digital pulse-width modulators (DPWM), simplified discrete-time compensator schemes, and analog-to-digital (A/D) converters. Digital controllers can also offer advantages of lower sensitivity to parameter variations, programmability, and reduction or elimination of passive components, often without compromising dynamic performance, simplicity, or cost.